The present invention relates generally to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a transistor such as a vertical bipolar transistor, a field effect transistor or the like and its manufacturing method in which variation of electrical characteristic can be remarkably suppressed.
The inventor of the present invention have proposed a vertical bipolar transistor and its manufacturing method which vertical bipolar transistor has a high cut-off frequency and in which reliable interconnection between conductor films or regions can be attained, in Japanese Patent No.2,551,353. FIG. 16 is a rough sectional view of a conventional vertical bipolar transistor similar to the vertical bipolar transistor disclosed in Japanese Patent No.2,551,353.
In FIG. 16, reference number 201 shows a p-type silicon substrate which has a surface of (100) plane and an electrical resistivity of 10 to 20 xcexa3-cm. Two kinds of buried layers of a few micrometers in thickness are formed on the surface of the silicon substrate 1. The two kinds of buried layers are an n+ type buried layer 202a and a channel stopper p+ type buried layer 202b, which exist separately from each other. A collector nxe2x88x92 type epitaxial silicon layer 203 is formed on the surfaces of these buried layers and on the surface of an area of the silicon substrate 201 where these buried layers do not exist. A silicon oxide film 204 is selectively formed to the depth reaching the p+ type buried layer 202b, and the silicon oxide film 204 forms an element isolation film. An n+ type collector lead-out region 205 connected to the n+ type buried layer 202a is formed by doping impurities in high concentration into a part of the collector nxe2x88x92 type epitaxial silicon layer 203. The portions described so far are collectively called a silicon basic body 200.
A silicon oxide film 206 is formed on the silicon basic body 200, and a base electrode p+ type polysilicon film 207 is selectively formed on the silicon oxide film 206. And the base electrode polysilicon film 207 is covered with a silicon nitride film 208. An opening 301 is formed so as to penetrate the silicon nitride film 208 and the base electrode p+ type polysilicon film 207, and an opening 302 is formed so as to penetrate the silicon oxide film 206. A collector epitaxial silicon layer 203 is partially exposed by these openings. This first opening 301 formed in the polysilicon film 207 is projected horizontally over the opening 302 from the edge of the second opening 302. That is to say, the width of the second opening 302 is larger than the width of the first opening 301.
A p+ type single crystal silicon intrinsic base 211 is formed on the collector epitaxial silicon layer 203 which is exposed by the second opening 302. A p+ type polysilicon film 212 is formed on the side surface and the exposed lower surface of the base electrode polysilicon film 207. Thus, the p+ type polysilicon film 212 connects the base electrode polysilicon film 207 and the intrinsic base 211 to each other.
An n++ type single crystal silicon emitter region 215 is provided in the middle area on the p+ type single crystal silicon intrinsic base 211. A silicon oxide film 213 is formed so as to over the side wall of the opening. In the collector epitaxial silicon layer 203 directly under the base region and between the intrinsic base 211 and the n+ type buried layer 202a, there is formed an n type silicon collector region 214 in which the concentration of impurities is higher than that of impurities in the original collector epitaxial silicon layer 203. An emitter electrode n++ type polysilicon 216 is provided on the n++ type single crystal silicon emitter region 215. These regions are all covered with a silicon oxide film 217.
Moreover, contact holes 303a, 303b and 303c which penetrate the silicon oxide film 217 and, depending upon places, penetrates also the silicon nitride film 208 and the silicon oxide film 206 are formed. Also, a metal film of aluminum-based alloy and the like is formed so as to fill these contact holes 303a, 303b and 303c, and furthermore a patterning process is applied to this metal film to form an emitter electrode 218a, a base electrode 218b and a collector electrode 218c. These emitter electrode 218a, base electrode 218b and collector electrode 218c composed of aluminum-based alloy are respectively in contact with the emitter electrode polysilicon 216, base electrode polysilicon film 207 and collector lead-out region 205.
A vertical bipolar transistor of the above-mentioned configuration shown in FIG. 16 has an adequate high-speed operation characteristic, but has a problem of large variation or dispersion in an operating current. Concretely speaking, it can be explained as follows. In a bipolar transistor circuit, a differential transistor pair is formed by short-circuiting with each other the emitters of adjacent transistors. It is assumed that voltages to be applied to the bases so that the collector currents of the respective transistors of the differential transistor pair become equal to each other are respectively VB1 and VB2. If the absolute value of the difference between these voltages, namely, the absolute value of xe2x80x9cVB1xe2x88x92VB2xe2x80x9d is defined as xcex94VB, the smaller this xcex94VB is, the more stable the circuit operation becomes. The reason is that in case that some number of stages of differential transistor pairs are combined inside the circuit, necessary input potentials vary due to occurrence of changeover among the differential transistor pairs. A vertical type bipolar transistor of the above-mentioned configuration shown in FIG. 16 has a large value of this xcex94VB.
On the other hand, in a vertical bipolar transistor disclosed in Japanese Patent No.2,551,353, such a problem does not occur. This is because, the side surface of a base electrode polysilicon film is completely covered with an insulating film such as a silicon nitride film. However, in a vertical bipolar transistor disclosed in Japanese Patent No.2,551,353, the film thickness WH of an intrinsic base single crystal film formed by a selective crystal growth method is thinner than the spacing WI between the upper surface of the collector epitaxial silicon layer and the lower surface of the base electrode polysilicon film (WH less than WI). Therefore, if the film thickness of a polysilicon film which selectively crystal-grows on the lower surface of the base electrode polysilicon film becomes too thin, another problem may occur that the intrinsic base is not connected to the base electrode polysilicon film. Thus, in the vertical bipolar transistor disclosed in Japanese Patent No. 2,551,353, it is necessary to strictly control a manufacturing process to avoid occurrence of such problem, and it is difficult to easily improve manufacturing yield and manufacturing cost.
Also, in the vertical bipolar transistor disclosed in Japanese Patent No. 2,551,353, in order to surely contact the intrinsic base and the base electrode polysilicon film, it is possible to consider that the film thickness WH of an intrinsic base single crystal film formed by a selective crystal growth method can be made thicker than the spacing WI between the upper surface of the collector epitaxial silicon layer and the lower surface of the base electrode polysilicon film (WH greater than WI). However, in such case, it has been found that there is a possibility that the intrinsic base single crystal film directly contacts the silicon nitride film covering the side wall of the base electrode polysilicon film and, thereby, a leak current of the bipolar transistor increases. The reason for this is considered that when the intrinsic base single crystal film contacts the silicon nitride film; stress increases in the vicinity of the interface between the intrinsic base single crystal film and the silicon nitride film and, in an extreme case, crystal defect occurs in the proximity of the interface between the intrinsic base single crystal film and the silicon nitride film.
Hereupon, an object of the present invention is to provide a semiconductor device and its manufacturing method which can solve the above-mentioned problems in the prior art.
It is another object of the present invention to provide a semiconductor device whose electric characteristics do not vary largely and to provide a method of manufacturing such semiconductor device.
It is still another object of the present invention to provide a semiconductor device which has stable and superior electric characteristics and to provide a method of manufacturing such semiconductor device.
It is still another object of the present invention to provide a semiconductor device and its manufacturing method in which electrical contacts can be reliably formed.
It is still another object of the present invention to provide a semiconductor device and its manufacturing method in which manufacturing yield of the semiconductor device is improved.
It is still another object of the present invention to provide a semiconductor device and its manufacturing method in which electric characteristics of the semiconductor device do not vary and in which increase in a leak current of the semiconductor device can be avoided.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a single crystal semiconductor substrate of a first conductivity type; a first insulating film which is formed on the main surface of said single crystal semiconductor substrate and which has a first opening having a first width to expose a portion of said main surface of said single crystal semiconductor substrate; a first semiconductor layer formed on at least a portion of the first insulating film and having a second conductivity type opposite to the first conductivity type; a second insulating film formed on the first insulating film so as to cover the first semiconductor layer; a second opening which is formed so as to penetrate the first semiconductor layer and the second insulating film and which is positionally aligned with the first opening, the second opening having a second width which is less than the first width, so that the side surface of the first semiconductor layer corresponding to the inner wall surface of the second opening projects toward the inner portion of the first opening from the side surface of the first insulating film corresponding to the inner wall surface of the first opening; an insulating side wall spacer formed at least on a portion of the side surface of the first semiconductor layer or of the side surface of the second insulating film corresponding to the inner wall surface of the second opening so as to expose the lower portion of the side surface of the first semiconductor layer corresponding to the inner wall surface of the second opening; a second semiconductor layer composed of a single crystal semiconductor of the second conductivity type formed on the portion of the main surface of the single crystal semiconductor substrate exposed at the bottom surface of the first opening; a third semiconductor layer of the second conductivity type for joining the exposed lower portion of the side surface of the first semiconductor layer corresponding to the inner wall surface of the second opening, and a portion of the lower surface of the first semiconductor layer in the proximity of the side surface of the first semiconductor layer corresponding to the inner wall surface of the second opening, to the end portion of the second semiconductor layer; a fourth semiconductor layer of the first conductivity type formed at a region in the proximity of the upper surface of the second semiconductor layer; and a fifth semiconductor layer of the first conductivity type formed on the upper surface of the second semiconductor layer.
In this case, it is preferable that the thickness of the third semiconductor layer is smaller than the thickness of the insulating side wall spacer.
It is also preferable that the single crystal semiconductor substrate is made out of single crystal silicon, the first semiconductor layer is made out of polysilicon, the second semiconductor layer is made out of single crystal silicon, and the third and fifth semiconductor layers are made out of polysilicon.
It is further preferable that the single crystal semiconductor substrate is made out of single crystal silicon, the first semiconductor layer is made out of polysilicon, the second semiconductor layer is made out of single crystal SiGe, the third semiconductor layer is made out of polycrystalline SiGe, and the fifth semiconductor layer is made out of polysilicon.
It is advantageous that the single crystal semiconductor substrate is made out of single crystal silicon, the first semiconductor layer is made out of single crystal silicon, the second semiconductor layer is made out of single crystal silicon, the third semiconductor layer is made out of single crystal silicon, and the fifth semiconductor layer is made out of polysilicon.
It is also advantageous that the insulating side wall spacer is formed by a first insulating side wall spacer portion formed on a portion of the side surface of the first semiconductor layer and of the side surface of the second insulating film corresponding to the inner wall surface of the second opening so as to expose the lower portion of the side surface of the first semiconductor layer corresponding to the inner wall surface of the second opening, and a second insulating side wall spacer portion which is formed on the first insulating side wall spacer portion, and wherein the length of the second insulating side wall spacer portion along the direction parallel to the inner wall of the second opening is longer than the length of the first insulating side wall spacer portion along the direction parallel to the inner wall of the second opening.
It is also preferable that the semiconductor device further comprising: a third, insulating film which covers at least partially the insulating side wall spacer and the second semiconductor layer.
It is further preferable that at least a portion of the first semiconductor layer is made out of single crystal semiconductor, the second opening penetrates the portion made out of single crystal semiconductor of the first semiconductor layer, and the third semiconductor layer is made out of single crystal semiconductor.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a single crystal semiconductor substrate of a first conductivity type; a first insulating film formed on the main surface of the single crystal semiconductor substrate and having a first opening which exposes a portion of the main surface of the single crystal semiconductor substrate, the first opening having a first opening width; a first semiconductor layer of a second conductivity type opposite to the first conductivity type formed on at least a portion of the first insulating film, at least a portion of the first semiconductor layer being made out of single crystal semiconductor; a second insulating film formed on the first insulating film so as to cover the first semiconductor layer; a second opening formed so as to penetrate the first semiconductor layer and the second insulating film, be positionally aligned with the first opening, the second opening penetrating the portion made out of single crystal semiconductor of the first semiconductor layer and having a second opening width which is smaller than the first opening width, so that the side surface of the first semiconductor layer corresponding to the inner wall surface of the second opening projects toward the inside of the first opening from than the side surface of the first insulating film corresponding to the inner wall surface of the first opening; a second semiconductor layer made of single crystal semiconductor of the second conductivity type formed on the portion of the main surface of the single crystal semiconductor substrate which expose at the bottom surface of the first opening; a third semiconductor layer made of single crystal semiconductor of the second conductivity type for joining the side surface portion of the first semiconductor layer corresponding to the inner wall surface of the second opening, and the portion in the proximity of the side surface of the first semiconductor layer corresponding to the inner wall surface of the second opening in the lower surface of the first semiconductor layer, to the end portion of the second semiconductor layer; a fourth semiconductor layer of the first conductivity type formed at an area in the proximity of the upper surface of the second semiconductor layer; and a fifth semiconductor layer of the first conductivity type formed on the upper surface of the second semiconductor layer.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a single crystal semiconductor substrate of a first conductivity type; forming a first insulating film on the main surface of the single crystal semiconductor substrate; forming. a first semiconductor layer of a second conductivity type opposite to the first conductivity type on at least a portion the first insulating film; forming a second insulating film on the first insulating film so as to cover the first semiconductor layer; selectively removing the first semiconductor layer and the second insulating film to form a first opening, the first opening having a first opening width and, at the bottom surface of the first opening, a portion of the first insulating film being exposed; forming a third insulating film on the inner wall surface and the bottom surface of the first opening and on the upper surface of the second insulating film; forming a fourth insulating film on the third insulating film, the fourth insulating film being made of different material from that of the third insulating film; etching back the third and fourth insulating films, leaving an insulating film side wall spacer formed of portions of the third and fourth insulating film on the inner wall surface of the first opening, and removing other portions of the third and fourth insulating film; removing the portion of the first insulating film exposed in the first opening and the exposed portion of the third insulating film portion forming the insulating film side wall spacer and thereby forming a second opening, the second opening having a second opening width which is larger than the first opening width, a portion of the main surface of the single crystal semiconductor substrate being exposed at the bottom surface of the second opening, the side surface of the first semiconductor layer corresponding to the inner wall surface of the first opening projecting toward the inside portion of the second opening from the side surface of the first insulating film corresponding to the inner wall surface of the second opening, leaving at least a portion of the third insulating film portion forming the insulating film side wall spacer on the inner wall surface of the first opening, exposing the lower portion of the side surface of the first semiconductor layer corresponding to the inner wall surface of the first opening, and exposing a portion of the lower surface of the first semiconductor layer in the proximity of the side surface of the first semiconductor layer corresponding to the inner wall surface of the first opening; growing a second semiconductor layer made out of single crystal semiconductor of the second conductivity type on the portion of the main surface of the single crystal semiconductor substrate exposed at the bottom surface of the second opening, and growing a third semiconductor layer of the second conductivity type from the exposed lower portion of the side surface of the first semiconductor layer corresponding to the inner wall surface of the first opening and from the exposed portion of the lower surface of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer joining to each other; forming a fourth semiconductor layer of the first conductivity type on the upper surface of the second semiconductor layer; and forming a fifth semiconductor layer of the first conductivity type at the region in the proximity of the upper surface of the second semiconductor layer.
In this case, it is preferable that the thickness of the portion of the third semiconductor layer grown from the exposed lower portion of the side surface of the first semiconductor layer corresponding to the inner wall surface of the first opening along the direction perpendicular to the inner wall surface of the first opening is smaller than the thickness of the insulating film side wall spacer along the direction perpendicular to the inner wall surface of the first opening.
It is also preferable that the thickness of the insulating film side wall spacer along the direction perpendicular to the inner wall surface of the first opening is larger than the maximum value in the range of dispersion of the thickness of growth of the third semiconductor layer in the growing the third semiconductor layer.
It is further preferable that the thickness of the third insulating film formed in the forming the third insulating film is made thicker than the maximum value in the range of dispersion of the thickness of growth of the third semiconductor layer in the growing the third semiconductor layer.
It is advantageous that the thickness of growth of the second semiconductor layer in the growing the second semiconductor layer is made larger than the thickness of the first insulating film formed in the forming the first insulating film, and is made smaller than the sum of the thickness of the first insulating film formed in the forming the first insulating film and the thickness of the third insulating film formed in the forming the third insulating film.
It is also advantageous that the single crystal semiconductor substrate is formed out of single crystal silicon, the first semiconductor layer is formed out of polysilicon, the second semiconductor layer is formed out of single crystal silicon, and the third semiconductor layer is formed out of polysilicon.
It is further advantageous that the single crystal semiconductor substrate is formed out of single crystal silicon, the first semiconductor layer is formed out of polysilicon, the second semiconductor layer is formed out of single crystal SiGe, and the third semiconductor layer is formed out of polycrystalline SiGe.
It is preferable that the single crystal semiconductor substrate is formed out of single crystal silicon, the first semiconductor layer is formed out of single crystal silicon, the second semiconductor layer is formed out of single crystal silicon, and the third semiconductor layer is formed out of single crystal silicon.
It is also preferable that the fourth semiconductor layer is made out of polycrystalline semiconductor of the first conductivity type which includes impurities of the first conductivity type in a high concentration, and wherein, in the forming the fifth semiconductor layer of the first conductivity type at the region in the proximity of the upper surface of the second semiconductor layer, the fifth semiconductor layer of the first conductivity type is formed at the region in the proximity of the upper surface of the second semiconductor layer by diffusing the impurities of the first conductivity type from the fourth semiconductor layer into the second semiconductor layer.
It is further preferable that the method further comprising: forming a fifth insulating film which covers at least partially the remaining portion of the insulating film side wall spacer and the second semiconductor layer and which defines the exposed portion of the second semiconductor layer, after growing a second semiconductor layer made out of single crystal semiconductor of the second conductivity type on the portion of the main surface of the single crystal semiconductor substrate exposed at the bottom surface of the second opening, and growing a third semiconductor layer of the second conductivity type from the exposed lower portion of the side surface of the first semiconductor layer corresponding to the inner wall surface of the first opening and from the exposed portion of the lower surface of the first semiconductor layer, and before forming a fourth semiconductor layer of the first conductivity type on the upper surface of the second semiconductor layer; and wherein, in the forming a fourth semiconductor layer of the first conductivity type on the upper :surface of the second semiconductor layer, a fourth semiconductor layer made of polycrystalline semiconductor including impurities of the first conductivity type in a high concentration is formed on at least the exposed portion of the second semiconductor layer defined by the fifth insulating film.
It is preferable that the method of manufacturing a semiconductor device further comprising: single crystallizing at least a portion of the first semiconductor layer, after forming a first semiconductor layer of a second conductivity type opposite to the first conductivity type on at least a portion the first insulating film, and before forming a second insulating film on the first insulating film so as to cover the first semiconductor layer; and wherein the first opening is formed within the single-crystallized portion of the first semiconductor layer, and the third semiconductor layer is made out of single crystal semiconductor.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a single crystal semiconductor substrate of a first, conductivity type; forming a first insulating film on the main surface of the single crystal semiconductor substrate; forming: a first semiconductor layer of a second conductivity type opposite to the first conductivity type on at least a portion of the first insulating film; single crystallizing at least a portion of the first semiconductor layer; forming a second insulating film on the first insulating film so as to cover the first semiconductor layer; selectively removing the first semiconductor layer and the second insulating film and thereby forming a first opening, the first opening being formed within a single-crystallized portion of the first semiconductor layer and having a first opening width, and, at the bottom surface of the first opening, a portion of the first insulating film being exposed; removing the portion of the first insulating film exposed within the first opening and thereby forming a second opening in the first insulating film, the second opening having a second opening width which is larger than the first opening, a portion of the main surface of the single crystal semiconductor substrate being exposed at the bottom surface of the second opening, the side surface of the first semiconductor layer corresponding to the inner wall surface of the first opening projects toward inside of the second opening from the side surface of the first insulating film corresponding to the inner wall surface of the second opening, the side surface of the first semiconductor layer corresponding to the inner wall surface of the first opening being exposed, and a portion of the lower surface of the first semiconductor layer in the proximity of the side surface of the first semiconductor layer corresponding to the inner wall surface of first opening being exposed; growing a second semiconductor layer made out of single crystal semiconductor of the second conductivity type on the portion of the main surface of the single crystal semiconductor substrate exposed at the bottom surface of the second opening, and growing a third semiconductor layer made out of single crystal semiconductor of the second conductivity type on the exposed side surface portion of the first semiconductor layer corresponding to the inner wall surface of the first opening and on the exposed portion of the lower surface of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer joining to each other; forming a fourth semiconductor layer of the first conductivity type on the upper surface of the second semiconductor layer; and forming a fifth semiconductor layer of the first conductivity type at a region in the proximity of the upper surface of the second semiconductor layer.
Inventor of the present invention have studied the cause of the above-mentioned problems in the prior art. In the following, the cause is described with reference to a vertical bipolar transistor as an example, but with reference to a field effect transistor, it is possible to consider the cause in the same way.
FIGS. 17A through 17C and FIGS. 18A through 18C illustrate schematic partial cross sectional structures obtained during a conventional manufacturing process of a portion around the intrinsic base 211 in the conventional vertical bipolar transistor shown in FIG. 16. With reference to FIG. 17A, the collector epitaxial silicon layer 203 of the silicon basic body 200 is fabricated by using any appropriate method. On the collector epitaxial silicon layer 203, the silicon oxide film 206, the p+type base electrode polysilicon film 207 and the silicon nitride film 208 are formed in this order. In this case, the polysilicon film 207 is patterned in areas not shown in the drawing by using, for example, photolithography and etching, before forming the silicon nitride film 208.
Then, as shown in FIG. 17B, an opening 301 is formed so as to penetrate a silicon nitride film 208 and a polysilicon film 207 by using, for example, photolithography and etching. Also, as shown in FIG. 17C, an opening 302 is formed so as to penetrate a silicon oxide film 206 by using etching and the like. By these openings 301 and 302, a portion of the collector epitaxial layer 203, and a side wall surface portion 207a and a portion 207b of the lower surface of the base electrode polysilicon film 207 are exposed. Next, as., shown in FIG. 18A, a p+ type single crystal silicon intrinsic base 211 is formed on the exposed portion of the collector epitaxial silicon layer 203 by means of a vapor phase epitaxial growth method, and at the same time a p+ type polysilicon film 212 is formed on the exposed portion 207a of the side surface and the exposed portion 207b of the lower surface of the base electrode polysilicon film 207. Since the collector epitaxial silicon layer 203 is a single crystal, the p+ type single crystal intrinsic base 211 formed on the collector layer 203 becomes a single crystal in the same way. On the other hand, since the base electrode polysilicon film 207 is polycrystalline, the p+ type silicon film 212 formed on the exposed portion 207a of the side surface and the exposed portion 207b of the lower surface of the base electrode polysilicon film 207 becomes polycrystalline in the same way. Moreover, after a silicon oxide film has been formed so as to cover the whole area of the substrate, the silicon oxide film spacer 213 is formed so as to cover the inner side wall of the opening 301, by etching back of the silicon oxide film by means of an an isotropic etching process. After this, as shown in FIG. 18C, an n++ type emitter electrode polysilicon 216 is formed by depositing and patterning n++ polysilicon. By performing a heat treatment after this, an n type impurity inside the n++ type emitter electrode polysilicon 216 is diffused into the surface area of the p+ type single crystal silicon intrinsic base 211 and an n++ type single crystal silicon emitter region 215 is formed. Thereby, a structure shown in FIG. 18C is obtained.
Hereupon, the inventor considered on the base electrode polysilicon film 207 in detail. It has been reported that in case that nondoped or additive-free (namely, no impurity added) polysilicon is deposited at a temperature within a range from approximately 600 to 650 degrees Celsius, the grain size in the deposited polysilicon film is 0.03 to 0.3 xcexcm and its orientation is a {110}. And when impurities are doped into the polysilicon film and, thereafter, a heat treatment for activating impurity atoms is performed, the grain size in the polysilicon film becomes 0.5 to 3 xcexcm, namely, larger than the grain size immediately after deposition. On the other hand, as in case of forming the opening 301, direction of crystal lattice planes of exposed surface of each grain at the exposed portion 207a of the side surface of the polysilicon film 207 formed by almost vertically dry-etching the polysilicon film is a direction perpendicular to the {110} plane, but if higher order direction of lattice planes is also considered, countless directions may exist.
On the other hand, an emitter region needs to become various sizes depending on the circuit structure. For example, the longitudinal dimension of an emitter can become about 2 xcexcm to 16 xcexcm or 32 xcexcm. Moreover, it is preferable in design of a circuit that an effective emitter area corresponds to a designed emitter area and a collector current increases or decreases in proportion to the effective emitter area. And it is preferable that approximately the same collector currents flow through transistors having the same size.
In case that the longitudinal dimension of an emitter is small, a not so many number of crystal grains are exposed at the exposed portion 207a of the side surface of the polysilicon film 207. As described above, the direction of crystal lattice planes of the exposed surface of each crystal grain at the inner surface of the opening 301, that is, at the exposed portion 207a of the side surface of the polysilicon film 207 is the direction perpendicular to the {110} plane. However, when higher order direction of lattice planes is considered, there are various directions depending on the grains even in the same opening 301, and, also, when compared the directions with respect to a plurality of openings 301 with one another, there are different directions depending upon the respective openings 301. Epitaxial growth rate of silicon varies considerably depending upon the direction of crystal lattice planes of a surface which becomes a seed of growth. When compared the directions for every openings 301 with one another, especially in case of small openings 301, the directions of crystal lattice planes of grains exposed at the inner surface of the openings 301 are different from one another. As a result thereof, the thickness of the polysilicon film 212 epitaxially growing from the exposed portion 207a of the side surface and the exposed portion 207b of the lower surface of the base electrode polysilicon film 207, that is, the projection size WA considerably varies among openings 301.
That is to say, in a conventional example, an intrinsic base is formed by a selective epitaxial growth method in a condition where the side surface portion 207a of the base electrode polysilicon film 207 is completely exposed. Thus, the thickness WA of the polysilicon film 212 grown on the side surface portion 207a of the base electrode polysilicon film 207 varies among opening 301. Thereafter, a silicon oxide film is formed so as to cover the whole area of the substrate and then the silicon oxide film is etched back by means of an an isotropic etching process to form a silicon oxide film spacer 213 covering the inner side wall portion of the opening 301. In this case, even if the thickness of the silicon oxide film spacer 213 is constant, the thickness WA of the polysilicon film 212 varies among openings 301 and it is difficult to make it constant. As a result thereof, the size WB of the opening 304 defined by the silicon oxide film spacer 213 covering the inner side wall of the opening 301 varies among openings 301. That is to say, the exposed surface of a p+ type single crystal silicon intrinsic base 211 exposed by the opening 304 defined by the silicon oxide film spacer 213 varies in area. And by heat-treating an n++ type emitter electrode polysilicon 216 formed by depositing and patterning n++ polysilicon, an n type impurity inside the n++ type emitter electrode polysilicon 216 is diffused into the surface area of the p+ type single crystal silicon intrinsic base 211 and an n++ type single crystal silicon emitter region 215 is formed. Therefore, the n++ type single crystal silicon emitter region 215 also varies in size depending upon each opening 301. Namely, an emitter varies in area. As a result, it has become apparent that electric characteristics of a vertical bipolar transistor having such a constitution as described above and shown in FIG. 16 vary, and the above-mentioned xcex94VB becomes large.
Thereupon, the inventor of the present invention have invented a manufacturing method and a structure of a transistor which is not influenced by the variation in the thickness of a polysilicon film epitaxially grown selectively from the side surface of a base electrode polysilicon film and which varies little in electric characteristics.
That is to say, according to a feature of the present invention, an insulating side wall spacer is formed on a part of the side surface of a first semiconductor layer corresponding to a base electrode polysilicon film, the thickness of the insulating side wall spacer WD is made thicker than the maximum thickness WF within a range of variation of the thickness WE of a polycrystalline film grown on the side surface of the base electrode polysilicon film, that is, the maximum thickness of the polycrystalline film (namely, WD greater than WF).
By this feature, even in case that there is variation in thickness WE of a polycrystalline film epitaxial-grown on the side surface of a base electrode polysilicon film, namely, even in case that there is variation in size of a projecting portion of the polycrystalline film projecting inward an opening formed in the base electrode polysilicon film, the size of the opening WG in an intrinsic base on which an emitter electrode polysilicon is deposited is not regulated by the size of the projecting portion of the polycrystalline film projecting inward the opening formed in the base electrode polysilicon film but is regulated by the side wall formed on a part of the side surface of the base electrode polysilicon film. As a result, variation in area of an emitter is greatly suppressed and the influence on its electric characteristics is made less.
Moreover, according to another feature of the present invention, a first semiconductor layer corresponding to a base electrode polysilicon is single-crystallized. As a result thereof, variation in size of a projecting portion of a semiconductor film projecting inward the opening formed in the base electrode polysilicon film and variation in area of an emitter is greatly suppressed and its influence on the electric characteristics is made less.
Also, an intrinsic base and a base electrode polysilicon film can be connected to each other only by the growth of a single crystal, by making the thickness WH of an intrinsic base single crystal film formed by means of a selective crystal growth method thicker than the spacing WI between the upper surface of a collector epitaxial silicon layer and the lower surface of the base electrode polysilicon film (WH greater than WI). Therefore, it is possible to avoid such a problem that an intrinsic base is not connected to a base electrode polysilicon film as the problem in case of a vertical bipolar transistor disclosed in Japanese Patent No.2,551,353.
Furthermore, by setting the relation among WH, WI and the film thickness WC of an insulating film (which is other than silicon nitride) to first cover the side surface of the base electrode polysilicon film to be etched at the same time as when the surface of the collector epitaxial silicon layer is exposed by etching the insulating film immediately before its selective crystal growth as:
WI less than WH less than WI+WC,
the intrinsic base single crystal film is not directly in contact with a silicon nitride film. Thereby, it is possible to prevent the increase of such a leak current that should be taken into consideration in the design of a semiconductor device in case of a vertical bipolar transistor disclosed in Japanese Patent No.2,551,353.